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CAT24WC03/05
2K/4K-Bit Serial EEPROM with Partial Array Write Protection FEATURES
s 400 kHz I2C bus compatible* s 1.8 to 5.5 volt operation s Low power CMOS technology s Write protect feature s Self-timed write cycle with auto-clear s 1,000,000 Program/Erase cycles s 100 Year data retention
s 8-pin DIP, 8-pin SOIC, 8-lead MSOP and 8-pin
TSSOP Package temperature ranges
-Top 1/2 array protected when WP at VIH
s 16-Byte page write buffer
s Commercial, industrial and automotive s "Green" package options available
DESCRIPTION
The CAT24WC03/05 is a 2K/4K-bit Serial CMOS EEPROM internally organized as 256/512 words of 8 bits each. Catalyst's advanced CMOS technology substantially reduces device power requirements. The
PIN CONFIGURATION
DIP Package (P, L, GL)
A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA
MSOP Package (R, Z, GZ)
A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC A0 WP A1 SCL A2 SDA VSS
TSSOP Package (U, Y, GY)
1 2 3 4 8 7 6 5
PIN FUNCTIONS
Pin Name A0, A1, A2 SDA SCL WP VCC VSS
i D
c s
Serial Clock Ground
i t n o
A0 A1 A2 VSS 1 2 3 4 8 7 6 5
SOIC Package (J, W, GW)
VCC WP SCL SDA
u n
VCC VSS VCC WP SCL SDA SDA WP
CAT24WC03/05 features a 16-byte page write buffer. The device operates via the I2C bus serial interface, has a special write protection feature, and is available in 8pin DIP or 8-pin SOIC packages.
BLOCK DIAGRAM
EXTERNAL LOAD DOUT ACK SENSE AMPS SHIFT REGISTERS
d e
a P
ts r
COLUMN DECODERS
WORD ADDRESS BUFFERS
START/STOP LOGIC
XDEC CONTROL LOGIC
E2PROM
Function
DATA IN STORAGE
Device Address Inputs Serial Data/Address
HIGH VOLTAGE/ TIMING CONTROL SCL A0 A1 A2 STATE COUNTERS SLAVE ADDRESS COMPARATORS
Write Protect +1.8V to +5.5V Power Supply
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 1005, Rev. F
CAT24WC03/05
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. -55C to +125C Storage Temperature ....................... -65C to +150C Voltage on Any Pin with Respect to Ground(1) ........... -2.0V to +VCC + 2.0V VCC with Respect to Ground ............... -2.0V to +7.0V Package Power Dissipation Capability (Ta = 25C) .................................. 1.0W Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current(2) ........................ 100mA RELIABILITY CHARACTERISTICS Symbol NEND(3) TDR
(3) (3)
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Parameter Endurance Data Retention ESD Susceptibility Latch-up
Min. 1,000,000 100 2000 100
Max.
VZAP
ILTH(3)(4)
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +5.5V, unless otherwise specified.
Symbol ICC IS(5) ILI ILO VIL VIH VOL1 VOL2
Parameter
Power Supply Current
Standby Current (VCC = 5.0V) Input Leakage Current Output Leakage Current Input Low Voltage
Input High Voltage
CAPACITANCE TA = 25C, f = 1.0 MHz, VCC = 5V Symbol CI/O(3) CIN(3) Test Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL, WP)
Note: (1) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V. (5) Standby Current (ISB) = 0A (<900nA).
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Output Low Voltage (VCC = 3.0V) Output Low Voltage (VCC = 1.8V)
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i t n o
Min
u n
Limits Typ
d e
Max 3 0 10 10 VCC x 0.3 VCC + 0.5 0.4 0.5
a P
Volts mA Units mA A A A V V V V
Units
Cycles/Byte Years
ts r
Test Conditions fSCL = 100 kHz VIN = GND or VCC VIN = GND to VCC VOUT = GND to VCC
-1
VCC x 0.7
IOL = 3 mA IOL = 1.5 mA
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24WC03/05
A.C. CHARACTERISTICS
VCC = +1.8V to +5.5V, unless otherwise specified.
Read & Write Cycle Limits CAT24WCXX-1.8 1.8V-5.5V Symbol FSCL TI
(1)
CAT24WCXX 2.5V-5.5V Min. Max. 100 200 3.5 4.7 4 4.7 4.5V-5.5V Min. Max. 400 Units kHz ns
Parameter Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out and ACK Out Time the Bus Must be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Data Out Hold Time Stop Condition Setup Time
Min.
Max. 10 0 200 3.5
tAA tBUF
(1)
4.7 4 4.7 4 4.7
tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF
(1) (1)
tSU:STO tDH
Power-Up Timing(1)(2) Symbol tPUR tPUW
Write Cycle Limits Symbol tWR
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus
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c s
Power-up to Read Operation Power-up to Write Operation
i t n o
Parameter
u n
50 1 4 100 Min
0
30 0
d e
4 4.7 0 50 4 100 Max 1 1 Typ
a P
1.2 0.6 1.2 0.6 0.6 0 50 0.6 100
ts r
200 1 s s s s s s ns ns 0.3 300 s ns s ns
1 300
Units ms ms
Parameter
Max 10
Units ms
Write Cycle Time
interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 1005, Rev. F
CAT24WC03/05
FUNCTIONAL DESCRIPTION
The CAT24WC03/05 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24WC03/05 operates as a Slave device. Both the Master and Slave devices can operate as either transmitter or receiver, but the Master device controls which mode is activated. A maximum of 8 devices (24WC03) and 4 devices (24WC05) may be connected to the bus as determined by the device address inputs A0, A1, and A2.
clock all data transfers into or out of the device. This is an input pin. SDA: Serial Data/Address The CAT24WC03/05 bidirectional serial data/address pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. A0, A1, A2: Device Address Inputs These inputs set device address when cascading multiple devices. When these pins are left floating the default values are zeros.
PIN DESCRIPTIONS
SCL: Serial Clock The CAT24WC03/05 serial clock input pin is used to Figure 1. Bus Timing
A maximum of eight devices can be cascaded when using the CAT24WC03. All three address pins are used for CAT24WC03. If only one CAT24WC03 is addressed on the bus, all three address pins (A0, A1, and A2) can be left floating or connected to VSS.
Figure 2. Write Cycle Timing
Figure 3. Start/Stop Timing
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24WC03/05
A total of four devices can be addressed on a single bus when using the CAT24WC05 device. Only A1 and A2 address pins are used with this device. The A0 address pin is a no connect pin and can be tied to VSS or left floating. If only one CAT24WC05 is being addressed on the bus, the address pins (A1 and A2) can be left floating or connected to VSS. WP: Write Protect If the WP pin is tied to VCC the upper half of memory array becomes Write Protected (READ only)(locations 80H to FFH for the CAT24WC03 and locations 100H to 1FFH for the CAT24WC05). When the WP pin is tied to VSS or left floating normal read/write operations are allowed to the device.
STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010 for the CAT24WC03/05 (see Fig. 5). The next three significant bits (A2, A1, A0) are the device address bits and define which device or which part of the device the Master is accessing. Up to eight CAT24WC03 and four CAT24WC05 can be individually addressed by the system. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT24WC03/05 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24WC03/05 then performs a Read or Write operation depending on the state of the R/W bit. Acknowledge
I2C BUS PROTOCOL
The following defines the features of the I2C bus protocol: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition
The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24WC03/05 monitor the SDA and SCL lines and will not respond until this condition is met.
Figure 4. Acknowledge Timing
Figure 5. Slave Address Bits
24WC03 24WC05
1 1 0 0 1 1 0 0 A2 A2 A1 A1 A0 a8 R/W R/W
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SCL FROM MASTER
DATA OUTPUT FROM TRANSMITTER
i t n o
START
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After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data.
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8
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9
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1
DATA OUTPUT FROM RECEIVER ACKNOWLEDGE
* A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device. ** a8 corresponds to the address of the memory array address word. ***A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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CAT24WC03/05
The CAT24WC03/05 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. When the CAT24WC03/05 is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24WC03/05 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. The CAT24WC03/05 writes up to 16 bytes of data in a single write cycle, using the Page Write operation. The Page Write operation is initiated in the same manner as the Byte Write operation; however, instead of terminating after the initial word is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted, the CAT24WC03/05 will respond with an acknowledge and internally increment the low order address bits by one. The high order bits remain unchanged.
WRITE OPERATIONS
Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the CAT24WC03/05. After receiving another acknowledge from the Slave, the Master device transmits the data byte to be written into the addressed memory location. The CAT24WC03/05 acknowledge once more and the Master generates the STOP condition, at which time the device begins its internal programming cycle to nonvolatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device. Page Write Figure 6. Byte Write Timing
If the Master transmits more than 16 bytes prior to sending the STOP condition, the address counter `wraps around', and previously transmitted data will be overwritten. Once all 16 bytes are received and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point all received data is written to the CAT24WC03/05 in a single write cycle. Acknowledge Polling
Figure 7. Page Write Timing
S T A R T
i D
c s
S
BUS ACTIVITY: MASTER
SDA LINE
i t n o
S T A R T SLAVE ADDRESS S
u n
BYTE ADDRESS
The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, the CAT24WC03/05 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT24WC03/05 is still busy with the write operation, no ACK will be returned. If the CAT24WC03/05 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation.
d e
DATA
a P
S T O P P
ts r
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS
BYTE ADDRESS (n)
DATA n
DATA n+1
DATA n+P
S T O P P
A C K
A C K
A C K
A C K
A C K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24WC03/05
WRITE PROTECTION
The Write Protection feature allows the user to protect against inadvertent programming of the memory array. If the WP pin is tied to VCC, the upper half (locations 80H to FFH for CAT24WC03 and locations 100H to 1FFH for CAT24WC05) of the memory array is protected and becomes read only. The CAT24WC03/05 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device's failure to send an acknowledge after the first byte of data is received.
In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N+1. If N=E (where E = 255 for the CAT24WC03 and 511 for the CAT24WC05), then the counter will `wrap around' to address 0 and continue to clock out data. After the CAT24WC03/05 receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Selective Read
READ OPERATIONS
The READ operation for the CAT24WC03/05 is initiated in the same manner as the write operation with the one exception that the R/W bit is set to a one. Three different READ operations are possible: Immediate Address READ, Selective READ and Sequential READ. Immediate Address Read The CAT24WC03/05 address counter contains the address of the last byte accessed incremented by one. Figure 8. Immediate Address Read Timing
Figure 9. Selective Read Timing
BUS ACTIVITY: MASTER SDA LINE S T A R T S A C K A C K SLAVE ADDRESS BYTE ADDRESS (n) S T A R T S A C K DATA n N O A C K SLAVE ADDRESS S T O P P
i D
c s
SCL SDA
i t n o
BUS ACTIVITY: MASTER SDA LINE S 8 8TH BIT
S T A R T
u n
SLAVE ADDRESS A C K 9
Selective READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a `dummy' write operation by sending the START condition, slave address and byte address of the location it wishes to read. After the CAT24WC03/05 acknowledge the word address, the Master device resends the START condition and the slave address, this time with the R/W bit set to one. The CAT24WC03/05 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition.
d e
DATA
a P
ts r
S T O P P N O A C K
DATA OUT
NO ACK
STOP
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 1005, Rev. F
CAT24WC03/05
Sequential Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT24WC03/05 sends the initial 8bit byte requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT24WC03/05 will continue to output an 8bit byte for each acknowledge sent by the Master. The operation is terminated when the Master fails to respond with an acknowledge, thus sending the STOP condition. Figure 10. Sequential Read Timing
BUS ACTIVITY: MASTER SDA LINE A C K A C K A C K A C K SLAVE ADDRESS DATA n DATA n+1 DATA n+2
The data being transmitted from the CAT24WC03/05 is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT24WC03/05 address bits so that the entire memory array can be read during one operation. If more than the E (where E = 255 for the CAT24WC03 and 511 for the CAT24WC05) bytes are read out, the counter will "wrap around" and continue to clock out data bytes.
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DATA n+x N O A C K
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24WC03/05
8-LEAD 300 MIL WIDE PLASTIC DIP (P, L, GL)
0.245 (6.17) 0.295 (7.49)
0.355 (9.02) 0.400 (10.16) 0.120 (3.05) 0.150 (3.81) 0.180 (4.57) MAX
0.300 (7.62) 0.325 (8.26)
0.015 (0.38)
0.110 (2.79) 0.150 (3.81)
0.100 (2.54) BSC 0.045 (1.14) 0.060 (1.52) 0.014 (0.36) 0.022 (0.56)
Notes: 1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters.
8-LEAD 150 MIL WIDE SOIC (J, W, GW)
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i t n o
u n
0.1497 (3.80) 0.1574 (4.00) 0 --8
d e
0.310 (7.87) 0.380 (9.65)
a P
ts r
0.2284 (5.80) 0.2440 (6.20)
0.1890 (4.80) 0.1968 (5.00)
0.0099 (0.25) X 45 0.0196 (0.50) 0.0532 (1.35) 0.0688 (1.75) 0.0075 (0.19) 0.0098 (0.25)
0.050 (1.27) BSC 0.013 (0.33) 0.020 (0.51)
0.0040 (0.10) 0.0098 (0.25)
0.016 (0.40) 0.050 (1.27)
Notes: 1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters.
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 1005, Rev. F
CAT24WC03/05
8 LEAD MSOP (R, Z, GZ)
0.0150 0.0110 0.38 0.28
0.1970 0.1890
5.00 4.80
S
0.0256 [0.65] BSC
0.1220 0.1142
0.0433 [1.10] MAX.
0.0276 0.0157
Notes: (1) All dimensions are in mm Angles in degrees. 2 Does not include Mold Flash, Protrusion or Gate Burrs. Mold Flash, Protrusions or Gate Burrs shall not exceed 0.15 mm. per side. 3 Does not include Interlead Flash orProtrusion. Interlead Flash or Protrusion shall not exceed 0.25 mm per side. 4 Does not include Dambar Protrusion, allowable Dambar Protrusion shall be 0.08 mm. (5) This part is compliant with JEDEC Specification MO-187 Variations AA. (6) Lead span/stand off height/coplanarity are considered as special characteristics. (S) (7) Controlling dimensions in inches. [mm]
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0.70 0.40
c s
0.1220 0.1142
i t n o
3.10 2.90
0.039 [0.10] MAX.
u n
3.10 2.90 S 0.0059 0.0020
d e
0.0374 0.0295 S 0.23 0.13
PLATING
a P
0.38 0.28
WITH PLATING
ts r
0.95 0.75
0.15 0.05
0.0150 0.0110
0.0091 0.0051
WITH
0.0050 [0.127]
0 - 6
BASE METAL 0.0118 [0.30] REF.
SECTION A - A
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24WC03/05
8-LEAD TSSOP (U, Y, GY)
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 1005, Rev. F
CAT24WC03/05
ORDERING INFORMATION
Prefix CAT Device # 24WC03 J Suffix I -1.8 TE13 REV-C
Optional Company ID
Product Number 24WC03: 2K 24WC05: 4K
Temperature Range Blank = Commercial (0C to 70C) I = Industrial (-40C to 85C) A = Automotive (-40C to 105C) E = Extended (-40C to 125C)
Tape & Reel
Package P: PDIP J: SOIC, JEDEC R: MSOP U: TSSOP L: PDIP (Lead-free, Halogen-free) W: SOIC, JEDEC (Lead-free, Halogen-free) Z: MSOP (Lead-free, Halogen-free) Y: TSSOP (Lead-free, Halogen-free) GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating) GW: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating) GZ: MSOP (Lead-free, Halogen-free, NiPdAu lead plating) GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)
Operating Voltage Blank: 2.5V - 5.5V 1.8: 1.8V - 5.5V
Notes: (1) The device used in the above example is a CAT24WC03JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage, Tape & Reel)
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CAT24WC03/05
REVISION HISTORY
Date 7/24/2001 2/3/2004 04/18/04 Revision Comments A B C Initial issue Added: CAT24WC03 not recommended for new designs. See CAT24FC03 data sheet. Add Lead Free Logo Update Features Update Ordering Information Add Revision History Update Rev Number 05/18/04 D Delete: CAT24WC03 not recommended for new designs. See CAT24FC03 data sheet. Update Revision History Update Rev Number 06/07/04 08/12/05 E F Added Die Revision to Ordering Information Update Features Update Pin Functions Update Reliability Characteristics Update D.C. Operating Characteristics Update A.C. Characteristics Add Page Dimensions Update Ordering Information
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 1005, Rev. F
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Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000.
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Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.
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Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.caalyst-semiconductor.com
Publication #: Revison: Issue date:
1005 F 08/12/05

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